🎓 Final-year ECE undergrad @ Thapar Institute of Engineering & Technology
💡 Passionate about VLSI · SoC Design · Digital ASICs · Verification
🚀 Exploring FPGA design · RTL coding · Hardware Verification through projects & research
- 🔍 Love solving problems in digital logic design, SoC architecture, and verification
- ⚡ Enjoy experimenting with FPGA boards, AMBA protocols, and testbench automation
- 🌱 Always learning — from SystemVerilog & UVM to DFT & Physical Design
- 📝 Co-authored research work on efficient FFT processors, submitted to a national VLSI conference
| 🔹 MIPS32 Pipeline Processor 5-stage pipelined CPU in Verilog; verified with assembly testcases |
🔹 UART with FIFO Buffer UART with configurable baud rate & FIFO using Vivado IP; debugged on FPGA |
| 🔹 SPI Protocol Verification SystemVerilog RTL + layered verification testbench (UVM-style) |
🔹 Traffic Light Controller (FSM) FSM-based 4-way controller simulated & implemented on FPGA |
👉 Explore more in my repositories
✅ Completed VSD Physical Design Flow & UVM Essentials courses
✅ Built regression automation using Tcl/Python scripting
✅ Diving into low-power design techniques and SoC verification