As a final-year Electrical & Electronics Engineering student with a Minor in Computer Science, my primary passion lies in the world of computer architecture and RTL design. I am driven by the challenge of designing digital systems from the ground up—from writing Verilog for custom processors to verifying logic on FPGAs. While I enjoy building full-stack applications, my core focus is on the hardware that makes it all possible
- 🔭 I’m currently exploring advanced RTL design for FPGAs and digital verification methodologies.
- 🌱 My core interests are CPU Architecture, SoC Design, and High-Performance Computing.
- ⚡ I believe in a meticulous approach to design, focusing on performance, efficiency, and robust verification.
Hardware & Architecture
Software & Full-Stack
Databases, Tools & Platforms
A selection of projects showcasing my experience in RTL Design and Verification.
NOC MetaPyUVM - Network-on-Chip Testbench
A comprehensive Python-based testbench for Network-on-Chip (NOC) verification using PyUVM and Cocotb frameworks.
Fault-Tolerant RISC-V Processor (Verilog)
A fault-tolerant, pipelined RISC-V processor featuring Triple Modular Redundancy (TMR) and SECDED memory protection. A deep dive into reliable computer architecture, designed for synthesis and verification.
MIPS 32-Bit Pipelined CPU (Verilog)
A custom 32-bit pipelined RISC processor in Verilog, featuring a 5-stage pipeline, hazard detection, and data forwarding. This project demonstrates core CPU concepts and was verified using Python testbenches.
Asynchronous and Synchronous FIFO
FIFO stands for "First-In, First-Out." It is a type of data structure or buffer in which the first data element added (the "first in") is the first one to be removed (the "first out"). This structure is commonly used in scenarios where order of operations is important.