This project focuses on the design and implementation of an optimized 64-bit priority encoder integrated with a cryptographic engine using Verilog HDL. The system efficiently identifies the highest-priority active input from a 64-bit input vector and securely processes the output using cryptographic logic.

The design emphasizes speed optimization, reduced hardware complexity, and secure data handling, making it suitable for digital systems and hardware security applications.

• 64-bit priority encoding with optimized logic
• Fast and efficient input detection
• Integration with a cryptographic processing block
• Modular and scalable Verilog design
• Suitable for FPGA and VLSI implementations

1. A 64-bit input vector is applied to the priority encoder.
2. The encoder determines the highest-priority active bit.
3. The encoded output is forwarded to the cryptographic engine.
4. Cryptographic logic processes the encoded data.
5. Final output is generated securely and efficiently.

• Verilog HDL
• Digital Logic Design
• VLSI Concepts
• Hardware Security
• FPGA Design Flow

• Xilinx Vivado
• ModelSim (for simulation)
• GTKWave (for waveform analysis)

• Processor interrupt handling
• Hardware security modules
• Digital communication systems
• Cryptographic hardware accelerators
• FPGA-based control systems

• Power optimization techniques
• Support for wider input sizes
• Advanced cryptographic algorithms
• ASIC-level optimization

Varri Sneha
B.Tech – Electronics and Communication Engineering
IIIT Manipur