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AionCore - RT Microkernel

A real-time microkernel with units, capabilities, and message-passing designed from the ground up for:

  • Hard real-time guarantees
  • Multi-core scalability
  • Capability-based security
  • Userspace services
  • Formal verification potential

Quick Start

# Build
make

# Run in QEMU
make run

# Clean
make clean

First Boot

AionCore First Boot

AionCore v0.1.0 booting in QEMU - showing HAL initialization, timer calibration, and real-time tick updates

Current Status

Phase 1: βœ… Foundation complete (HAL, per-CPU, IDT, VGA) Phase 2: βœ… Complete (Timer, PMM, MMU/paging) Phase 3.1: βœ… Preemptive multitasking working! Phase 3.2: βœ… Syscalls complete (INT 0x80) Phase 3.3: βœ… Ring 3 userspace working! Phase 3.4: πŸ”¨ Next up (Per-task address spaces)

πŸ‘‰ See CURRENT_WORK.md for today's status and next steps.

Architecture

This is not a UNIX clone. Key concepts:

  • Units: Isolated execution containers (not "processes")
  • Threads: Execute within units
  • Channels: Message-passing IPC
  • Capabilities: Explicit access rights, no ambient authority
  • No POSIX in kernel: POSIX is a userspace personality

The kernel is <10K LOC and provides only core primitives. Everything else (filesystems, drivers, services) runs in userspace.

Documentation

πŸ“‚ docs/ - All documentation

Start here:

Design details:

Development:

Project Structure

kernel/
β”œβ”€β”€ CURRENT_WORK.md          ← Start here for current status
β”œβ”€β”€ DEVELOPMENT_LOG.md       ← Development narrative and history
β”œβ”€β”€ README.md                ← You are here
β”œβ”€β”€ Makefile                 ← Build system
β”œβ”€β”€ grub.cfg                 ← GRUB configuration
β”œβ”€β”€ .claude.md               ← Development workflow rules
β”‚
β”œβ”€β”€ arch/x86/                ← x86-specific code
β”‚   β”œβ”€β”€ boot.s               β”‚  Multiboot entry point
β”‚   β”œβ”€β”€ hal.c                β”‚  Hardware abstraction layer
β”‚   β”œβ”€β”€ gdt.c                β”‚  GDT and TSS setup
β”‚   β”œβ”€β”€ idt.c / idt_asm.s    β”‚  Interrupt handling
β”‚   β”œβ”€β”€ timer.c              β”‚  PIT + TSC calibration
β”‚   β”œβ”€β”€ mmu.c                β”‚  x86 paging/MMU
β”‚   β”œβ”€β”€ context.s            β”‚  Hybrid context switch (kernel/user)
β”‚   β”œβ”€β”€ syscall.s            β”‚  INT 0x80 syscall entry
β”‚   β”œβ”€β”€ user_test.s          β”‚  Ring 3 test program
β”‚   └── linker.ld            β”‚  Memory layout
β”‚
β”œβ”€β”€ core/                    ← Architecture-neutral kernel core
β”‚   β”œβ”€β”€ init.c               β”‚  Kernel entry and initialization
β”‚   β”œβ”€β”€ percpu.c             β”‚  Per-CPU data structures
β”‚   β”œβ”€β”€ task.c               β”‚  Task management
β”‚   β”œβ”€β”€ scheduler.c          β”‚  O(1) priority scheduler
β”‚   β”œβ”€β”€ syscall.c            β”‚  Syscall dispatcher and implementations
β”‚   β”œβ”€β”€ user.c               β”‚  Userspace task creation
β”‚   β”œβ”€β”€ console.c            β”‚  Console multiplexer
β”‚   └── ktest.c              β”‚  Unit testing framework
β”‚
β”œβ”€β”€ drivers/                 ← Device drivers (modular)
β”‚   β”œβ”€β”€ vga/                 β”‚  VGA text mode driver
β”‚   β”‚   β”œβ”€β”€ vga.c            β”‚  VGA subsystem
β”‚   β”‚   β”œβ”€β”€ vga_text.c       β”‚  Text mode implementation
β”‚   β”‚   └── vga_console.c    β”‚  Console backend
β”‚   └── serial/              β”‚  Serial UART driver
β”‚       β”œβ”€β”€ uart.c           β”‚  8250/16550 driver
β”‚       └── serial_console.c β”‚  Console backend
β”‚
β”œβ”€β”€ lib/                     ← Kernel library functions
β”‚   └── string.c             β”‚  Safe string operations
β”‚
β”œβ”€β”€ mm/                      ← Memory management
β”‚   └── pmm.c                β”‚  Physical memory manager
β”‚
β”œβ”€β”€ tests/                   ← Unit tests
β”‚   β”œβ”€β”€ test_main.c          β”‚  Host test runner
β”‚   β”œβ”€β”€ pmm_test.c           β”‚  PMM unit tests
β”‚   β”œβ”€β”€ scheduler_test.c     β”‚  Scheduler unit tests
β”‚   └── kprintf_test.c       β”‚  kprintf unit tests
β”‚
β”œβ”€β”€ include/                 ← Public headers
β”‚   β”œβ”€β”€ kernel/              β”‚  Core kernel headers
β”‚   β”‚   β”œβ”€β”€ hal.h            β”‚  HAL interface
β”‚   β”‚   β”œβ”€β”€ idt.h            β”‚  Interrupt handling
β”‚   β”‚   β”œβ”€β”€ percpu.h         β”‚  Per-CPU data
β”‚   β”‚   β”œβ”€β”€ task.h           β”‚  Task management
β”‚   β”‚   β”œβ”€β”€ scheduler.h      β”‚  Scheduler
β”‚   β”‚   β”œβ”€β”€ timer.h          β”‚  Timer subsystem
β”‚   β”‚   β”œβ”€β”€ pmm.h            β”‚  Physical memory
β”‚   β”‚   β”œβ”€β”€ mmu.h            β”‚  Virtual memory
β”‚   β”‚   β”œβ”€β”€ console.h        β”‚  Console multiplexer
β”‚   β”‚   └── types.h          β”‚  Type definitions
β”‚   β”œβ”€β”€ drivers/             β”‚  Driver interfaces
β”‚   β”‚   β”œβ”€β”€ vga.h            β”‚  VGA driver
β”‚   β”‚   └── serial.h         β”‚  Serial driver
β”‚   └── lib/                 β”‚  Library headers
β”‚       └── string.h         β”‚  String functions
β”‚
└── docs/                    ← Documentation
    β”œβ”€β”€ DOCS.md              β”‚  Documentation index
    β”œβ”€β”€ VISION.md            β”‚  Long-term vision
    β”œβ”€β”€ IMPLEMENTATION_ROADMAP.md  β”‚  Development plan
    β”œβ”€β”€ UNITS_ARCHITECTURE.md      β”‚  Units model details
    β”œβ”€β”€ RT_CONSTRAINTS.md          β”‚  RT requirements
    β”œβ”€β”€ FORMAL_VERIFICATION.md     β”‚  Verification strategy
    β”œβ”€β”€ MULTI_ARCH.md              β”‚  Multi-arch support
    β”œβ”€β”€ ARCHITECTURE.md            β”‚  Design principles
    └── ISSUES.md                  β”‚  Issue tracking

Features

βœ… Implemented (Phases 1-3.1)

Foundation & HAL:

  • Hardware Abstraction Layer (HAL)
  • Per-CPU data structures (cache-line aligned)
  • IDT and interrupt handling (256 entries)
  • Exception handlers with register dumps
  • Safe string library (no strcpy/strcat)
  • Lock-free per-CPU tracing

Drivers & Console:

  • Modular VGA driver with kprintf
  • Serial UART driver (8250/16550, 115200 baud)
  • Console multiplexer (VGA + serial dual output)

Timing:

  • PIT timer with TSC calibration (1000 Hz, microsecond precision)

Memory Management:

  • Physical memory manager (PMM, bitmap-based)
  • MMU with x86 paging (identity-mapped kernel)
  • O(1) page map/unmap operations

Tasks & Scheduling:

  • Task management (create, destroy, yield)
  • O(1) scheduler (256 priority levels)
  • Context switching (< 200 cycles, full EFLAGS/segment restore)
  • Timer-driven preemptive multitasking (1000 Hz)
  • Priority-based preemption with round-robin

Testing & Development:

  • Unit testing framework (ktest)
  • Host-side unit tests for logic validation
  • Direct QEMU kernel boot (5x faster iteration)

πŸ”¨ In Progress (Phase 3.2)

  • Syscall mechanism (INT 0x80 or SYSENTER/SYSEXIT)
  • GDT with ring 3 segments
  • TSS for kernel stack switching
  • First userspace task (ring 3 transition)

πŸ“‹ Planned

  • Phase 3: Tasks, threads, scheduler, syscalls
  • Phase 4: IPC, capabilities, message passing
  • Phase 5: Userspace services
  • Phase 6: SMP/multicore
  • Phase 7: More userspace servers
  • Phase 8: Advanced features (shared memory, IRQ caps)

Design Principles

  1. Microkernel First - IPC and capabilities early, not late
  2. Real-Time Throughout - Every path has bounded time
  3. Userspace by Default - If it can be userspace, it must be
  4. Per-CPU Everything - Minimize locking, maximize parallelism
  5. Capability Security - No ambient authority
  6. Small TCB - <10K LOC for verification
  7. No POSIX in Kernel - Build as userspace personality

See docs/ARCHITECTURE.md for detailed rationale.

Real-Time Guarantees

Operation Target Status
Context switch <200 cycles Phase 3
Scheduler pick <100 cycles Phase 3
IPC send/recv <500 cycles Phase 4
IRQ dispatch <100 cycles βœ… Ready
Interrupt latency <10Β΅s Phase 2

See docs/RT_CONSTRAINTS.md for full requirements.

Building

Requirements

  • i686-elf cross-compiler
  • GNU Make
  • GRUB tools (grub-mkrescue)
  • QEMU (for testing)

Build Commands

# Full build
make

# Clean build
make clean && make

# Run in QEMU (direct kernel boot - fast)
make run

# Run in QEMU (GRUB/ISO boot)
make run-iso

# Run in QEMU (terminal only, no GUI)
make run-nographic

# Build and run with unit tests
make test

# Show help
make help

Development

Daily workflow:

  1. Check CURRENT_WORK.md for current status
  2. Read DEVELOPMENT_LOG.md to understand context and history
  3. Follow docs/IMPLEMENTATION_ROADMAP.md for APIs
  4. Follow docs/KERNEL_C_STYLE.md before/after coding
  5. Follow docs/RT_CONSTRAINTS.md for performance
  6. Update docs when completing work

Coding guidelines:

  • Small functions (<50 LOC)
  • No undefined behavior
  • Bounded execution time (O(1) in RT paths)
  • Document invariants
  • Keep arch code in arch/
  • All hardware access via HAL
  • Write unit tests for new subsystems

See docs/KERNEL_C_STYLE.md for complete coding standards.

Contributing

This is an experimental kernel exploring modern OS design patterns. Key areas:

  • Capability-based security
  • Message-passing IPC
  • Real-time scheduling
  • Lock-free per-CPU patterns
  • Formal verification techniques

See docs/VISION.md for the full design philosophy.

License

MIT License - Copyright (c) 2025 sistemica GmbH

See LICENSE for full details.

References

Influences:

  • seL4 - Formally verified microkernel
  • Fuchsia - Capability-based Zircon kernel
  • QNX - Real-time microkernel
  • MINIX - Pioneering microkernel design

Our twist:

  • Units instead of processes
  • Built for RT from day one
  • Designed for formal verification
  • No POSIX in kernel
  • Per-CPU lock-free patterns
  • Message-passing by default

Start exploring: Read CURRENT_WORK.md for what's happening now!

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AionCore - Real-time microkernel with units, capabilities, and message-passing. Part of the Aion operating system family.

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