I'm Pin-Hao, a Digital IC / RTL enthusiast from NCHU EE.

• Focus: Verilog/SystemVerilog RTL · AXI4/AXI-Stream/AXI-Lite ·
• Toolchain: Vivado · ModelSim· Python (Jupyter) · C++/OpenCV · Git/Linux
• Recent: Built an FPGA-based FAST corner detection prototype.

• RTL: Verilog, SystemVerilog
• FPGA/SoC: PYNQ-ZU / Zynq MPSoC

FAST Corner Detection Accelerator (FPGA · RTL)
Streaming circle-16 test + NMS, II=1 @ 100 MHz, ORBextractor-friendly output.
➡ Repo: https://github.com/ashs810061/FPGA-FAST-Corner-Detector

• Email: [email protected]