FPGA-based closed-loop eBike control system implemented in SystemVerilog for the DE0-Nano platform.

This repository contains class exercises, module prototypes, synthesis artifacts, and the integrated team project for an eBike controller. The final design combines sensing, estimation, control, motor drive, and telemetry into one top-level FPGA implementation.

At a high level, the controller:

• Samples rider and system signals (brake, torque, motor current, battery voltage, cadence, inertial sensor).
• Conditions and interprets sensor data.
• Computes an assist target and closes the loop with PID control.
• Generates BLDC motor drive signals through PWM and commutation logic.
• Exposes UART telemetry for debugging and validation.

Main datapath blocks shown in the architecture:

• A2D: SPI-connected ADC acquisition.
• sensorCondition: filtering/normalization of cadence and inertial signals.
• desiredDrive: rider intent + mode logic.
• PID: closed-loop assist control.
• MtrDrv/PWM/brushless: BLDC gate-generation path.
• Telemetry/UART: transmit debug and runtime status.

Based on the integrated design files in rtl/controller and supporting labs, the expected implementation scope is:

• Platform target:

  • DE0-Nano FPGA deployment.
  • Synthesizable RTL in SystemVerilog.

• Sensor interfaces:

  • External ADC over SPI (SPI_mnrch, SPI_ADC128S, A2D_intf).
  • Cadence and inertial interface chain (cadence_meas, cadence_filt, inert_intf, inertial_integrator).

• Control chain:

  • Assist request generation (desiredDrive).
  • Feedback control using PID.
  • Saturation/conditioning support (incline_sat, related conditioning blocks).

• Motor drive:

  • PWM generation and dead-time safe switching (PWM, nonoverlap).
  • Brushless commutation and gate drive (brushless, mtr_drv).

• System features:

  • Push-button handling and synchronization (PB_*, reset_synch, PB_release, PB_rise).
  • Telemetry output over UART (telemetry, UART_tx, UART_rcv).

• Verification:

  • Standalone and integrated simulation benches (*_tb.sv) for interface-level and system-level behavior.

Top-level directories and their roles:

• rtl/controller: integrated project RTL and testbenches (primary final design source).
• rtl/provided_files: starter/support files and legacy board project collateral.
• board/src: board-level bring-up HDL sources.
• board/config: Quartus board project configuration files.
• tests/board_tb: board-focused testbenches and shared TB helper files.
• tests/sim_scripts/board: simulation waveform and board test scripts.
• labs/classwork: incremental lab modules and focused exercises.
• synthesis/design_vision_files: synthesis reports, constraints, and generated implementation artifacts.
• synthesis/board_test_artifacts: generated Quartus outputs and backup files moved out of board sources.
• docs/assets: diagrams and static documentation images.

Notable subfolders in labs/classwork/:

• A2D_synthesis_files, ex_11_SPI: SPI/ADC interface development.
• sensorCondition, desiredDrive, PID_A2D: control and signal-conditioning path pieces.
• exercise13_complete, exercise16_mtr_drv_demo, mtr_drv, PWM, nonoverlap: motor-drive pipeline components.

• Quartus project files (.qpf, .qsf) are included in several folders for synthesis and board mapping.
• Most major modules have corresponding simulation testbenches (*_tb.sv).
• eBike_tb.sv and related physics/analog model files provide integrated behavioral verification.

• Dustin Nguyen
• Shane O'Donnell
• Quinn Johnson

This project is licensed under the MIT License.