Lift is a novel approach to achieving performance portability on parallel accelerators. Lift combines a high-level functional data parallel language with a system of rewrite rules which encode algorithmic and hardware-specific optimisation choices. Applications written in Lift are able to take advantage of GPUs (and in the future other accelerators), transparently from the user.
We are always looking for bright and enthusiastic researchers to join our team. We have funding opportunities for PhD studies and visits/internships both at the University of Edinburgh ([email protected]) and the University of Glasgow ([email protected]). Please feel free to contact us if you are interested.
The Lift source code is available at https://github.com/lift-project/lift.
Lift is open source software released under the permissive MIT license.
Starting from a single high-level program, our compiler automatically generates highly optimized and specialized matrix multiplication implementations. We group simple rewrite rules into more complex macro-rules, each describing a well-known optimization like tiling and register blocking in a composable way. Using an exploration strategy our compiler automatically generates 50,000 OpenCL kernels, each providing a differently optimized — but provably correct — implementation of matrix multiplication.
Making neural networks (NNs) performance-portable using Lift: implementing generic and NN-specific optimizations as rewrite rules for efficient hardware utilization; introducing traditional NN building blocks such as conv, norm and fully_connected for seamless integration of Lift with popular machine learning libraries.
Using Lift to create a high-level programming environment for Heterogeneous Computation, freeing the programmer from the burden of having to write complex device-specific code. This makes it possible to automatically identify parallelism in non-associative reductions and scans, hence enabling generation of efficient parallel implementations for GPUs.
We demonstrate that high level programming and high performance GPU execution for sparse, irregular problems are not mutually exclusive. Our insight is that this can be achieved by capturing sparsity and irregularity friendly implementations within the target space of a pattern-oriented, high-level compilation and transformation system. By working in a language rather than a library, we benefit from the ability to generate implementations by program-specific composition of building blocks which capture detailed, low-level implementation choices.
Simplified room acoustics simulations have been thoroughly investigated in Lift and a number of other 2D and 3D benchmarks have also been implemented. Current work also involves developing and formalising stencil optimisations for 3D codes, in particular 2.5D tiling, as well as ground penetrating radar algorithms. How to best abstract out absorbing boundary conditions needs to be investigated in more detail and primitives to accommodate these conditions need to be designed and added. Finally, a stencil-based DSL needs to be extended to compile into the Lift language.
Stencil computations are used in a wide range of applications from physical simulations to machine learning. Optimizing and tuning them for parallel hardware remains challenging. Lift is a new approach to achieving performance portability based on a small set of reusable parallel primitives. Its key novelty is encoding of optimization as a system of rewrite rules which are used to explore the optimization space. We extend Lift with support for stencil computations by adding a small number of primitives together with a few rewrite rules to achieve performance portability for stencil computations.
FPGAs are highly energy-efficient and offer a lot of flexibility to implement an application. With Lift, we want to exploit the FPGA's characteristics to lift the performance and energy-efficiency of neural network tasks. Starting from a high-level functional specification, the Lift compiler applies rewrite rules to explore different implementations and finally generates a low-level, optimised hardware design for FPGAs.
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Christophe Dubach
Michel Steuwer
Lu Li
Toomas Remmelg
Bastian Hagedorn
Larisa Stoltzfus
Federico Pizzuti
Naums Mogers
Andrej Ivanis
Christof Schlaak
Bastian Köpcke
Thomas Koehler
Adam Harries
Martin Kristien