A terminal UI for inspecting and modifying FPGA Control and Status Registers (CSRs) in real time. Load a register map from a SystemRDL (.rdl) or pre-exported JSON file, connect an FTDI module, and read/write registers directly from your terminal.

• Browse the full register hierarchy with field-level detail (bits, access type, reset value)
• Read individual registers or refresh the entire map at once
• Write registers with hex input
• Live connection status — reconnects automatically when the device is plugged in
• Optional auto-refresh on a configurable interval
• Fuzzy register search (/)
• Vim-style navigation (j/k, g/G)
• Supports FT2232H and FT4232H FTDI devices

• Rust toolchain (cargo)
• libftdi1 development library
  • Debian/Ubuntu: sudo apt install libftdi1-dev
  • Arch: sudo pacman -S libftdi
  • macOS: brew install libftdi
• uv (only needed for .rdl input — fetches systemrdl-compiler automatically on first use)

cargo build --release

The binary is at target/release/peakview.

peakview [OPTIONS] <REGISTERS>

<REGISTERS> is either a .rdl source file or a pre-exported .json file.

# Load from a SystemRDL file, FT4232H (default)
peakview registers.rdl

# Load from a pre-exported JSON, FT2232H
peakview --device-type ft2232h registers.json

# Auto-refresh every 500 ms
peakview --refresh 500 registers.rdl

peakView accepts two input formats:

SystemRDL (.rdl) — compiled at runtime via uv run --with systemrdl-compiler. No manual Python setup required; uv manages a throw-away virtual environment automatically.

JSON — a pre-exported register map. Use the bundled export script to generate one offline:

uv run --with systemrdl-compiler python3 peakview-backend/export_json.py registers.rdl > registers.json

An example register map (example_peak_rdl/spi.rdl) is included for testing without hardware.

Runtime warnings and errors are written to peakview.log in the working directory.