High throughput JPEG decoder in Verilog for FPGA
-
Updated
Mar 5, 2022 - Verilog
#
axi-stream
Here are 50 public repositories matching this topic...
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
-
Updated
Mar 26, 2026 - SystemVerilog
This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core
-
Updated
Mar 15, 2022 - Verilog
This project is designed to delay the output of the video stream in AXI-STREAM format.
-
Updated
Jul 14, 2024 - Verilog
Tutorials or projects example to use Vivado 2019.2 and Vitis
-
Updated
Oct 27, 2020 - VHDL
Various video processing projects will be shared here
-
Updated
May 26, 2020 - Jupyter Notebook
FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol
-
Updated
Dec 2, 2021 - SystemVerilog
Synchronous and Asynchronous FIFO with AXI interface
-
Updated
Nov 20, 2019 - SystemVerilog
A one-position buffer compatible with AXI Stream interface
-
Updated
May 23, 2023 - Tcl
FPGA benchmark of vectorized gradient descent on linear regression
-
Updated
Mar 27, 2026 - VHDL
An IP used for testing AXI stream protocols. It uses a LFSR to generate ready and valid signals
-
Updated
Aug 10, 2020 - Tcl
FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device
-
Updated
Feb 20, 2023 - C
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
embedded fpga hls xilinx vivado xilinx-fpga basys3 xilinx-vivado axi artix axi-stream vivado-ip-integrator artix-7 xilinx-hls vitis axi-lite xilinx-vitis vivado-vitis vitis-hls axi-memory-mapped
-
Updated
Nov 21, 2023 - TeX
Performance counter to measure latency between two AXI Stream interfaces with pattern matching as trigger.
-
Updated
Aug 3, 2023 - VHDL
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
embedded fpga hls xilinx vivado xilinx-fpga basys3 xilinx-vivado microblaze axi artix axi-stream vivado-ip-integrator artix-7 xilinx-hls vitis axi-lite xilinx-vitis vivado-vitis vitis-hls
-
Updated
Dec 3, 2023 - C
Event-based predictive vision RTL core in synthesizable Verilog, validated in Vivado as both a bare core and AXI-integrated evaluation shell.
fpga uav prediction predictive rtl verilog xilinx low-latency vivado neuromorphic-hardware dvs neuromorphic-computing axi-stream axi4 event-cameras drone-control
-
Updated
Apr 14, 2026 - Verilog
Fast bwa-mem dna matching algor implemented in system verilog, fully synthesizable.
-
Updated
Apr 9, 2022 - Stata
Improve this page
Add a description, image, and links to the axi-stream topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the axi-stream topic, visit your repo's landing page and select "manage topics."