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  • IIIT Hyderabad
  • India
  • 16:01 (UTC +05:30)

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Popular repositories Loading

  1. 5-bit-CLA 5-bit-CLA Public

    Transistor-level design of a 5-bit Carry Look-Ahead Adder using Static Manchester Carry Chain (MCC) with pre- and post-layout SPICE simulations and Magic layout in 180nm CMOS.

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  5. Probability-and-Random-Processes-IIITH Probability-and-Random-Processes-IIITH Public

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  6. riscv-pipeline-simulator riscv-pipeline-simulator Public

    A 5-stage pipelined RISC-V processor implemented in Verilog with hazard detection unit and data forwarding.

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