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IIIT Hyderabad
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5-bit-CLA
5-bit-CLA PublicTransistor-level design of a 5-bit Carry Look-Ahead Adder using Static Manchester Carry Chain (MCC) with pre- and post-layout SPICE simulations and Magic layout in 180nm CMOS.
Verilog
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signal-processing-course-project
signal-processing-course-project PublicSignal Processing Course Project
MATLAB
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non-ideal-sampling-reconstruction
non-ideal-sampling-reconstruction PublicReconstruction of band-limited signals sampled under non-ideal conditions, specifically sampling-time jitter, using sinc-based interpolation and matrix inversion methods implemented in MATLAB.
MATLAB
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VLSI-Design-IIITH
VLSI-Design-IIITH PublicAssignments, projects, question papers, textbooks, and reference material for VLSI Design course
Verilog
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Probability-and-Random-Processes-IIITH
Probability-and-Random-Processes-IIITH PublicAssignments, tutorials, question papers, textbooks, and reference materials for Probability and Random Processes course
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riscv-pipeline-simulator
riscv-pipeline-simulator PublicA 5-stage pipelined RISC-V processor implemented in Verilog with hazard detection unit and data forwarding.
Verilog
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