This repository contains the complete design, physical implementation, and verification of a high-speed 5-bit Carry Look-Ahead Adder (CLA) using a Static Manchester Carry Chain (MCC) implemented in 180nm CMOS technology.

The project follows the full VLSI design flow, including transistor-level schematic design, pre- and post-layout SPICE simulations, physical layout using Magic VLSI, and functional validation using Verilog and FPGA implementation.

Binary addition is a fundamental operation in digital systems and a critical component of Arithmetic Logic Units (ALUs). Conventional adders such as Ripple Carry Adders suffer from large propagation delays due to serial carry dependency.

This project addresses that limitation by implementing a Carry Look-Ahead Adder (CLA) accelerated using a Static Manchester Carry Chain (MCC), which enables fast parallel carry propagation while reducing delay, area, and parasitic effects.

• Generate (G), Propagate (P), and Delete (D) signals
• Parallel computation of carry bits
• Avoids large fan-in static CMOS gates

• Transmission-gate based carry propagation
• Eliminates long transistor stacks
• Maintains full rail-to-rail voltage swing
• Significantly reduces critical path delay

• Input and output register banks
• Implemented using Modified TSPC (MTSPC) D Flip-Flops

• Technology Node: TSMC 180nm CMOS
• Circuit Simulation: NGSpice
• Physical Layout & Extraction: Magic VLSI
• HDL: Verilog
• Hardware Validation: FPGA

1. Transistor-level functional verification using NGSpice
2. Post-layout simulation with parasitic extraction
3. Timing analysis (setup time, clock-to-Q delay, critical path)
4. Verilog RTL simulation
5. FPGA synthesis and hardware validation

• N. H. Weste and D. M. Harris, CMOS VLSI Design
• J. M. Rabaey, A. Chandrakasan, and B. Nikolić, Digital Integrated Circuits: A Design Perspective.